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cy7c1563xv18, cy7c1565xv18 72-mbit qdr ? ii+ xtreme sram four-word burst architecture (2.5 cycle read latency) cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-70205 rev. *b revised june 22, 2012 72-mbit qdr ? ii+ xtreme sram four-word burst architecture (2.5 cycle read latency) features separate independent read and write data ports ? supports concurrent transactions 633 mhz clock for high bandwidth four-word burst for reducing address bus frequency double data rate (ddr) interfaces on both read and write ports (data transferred at 1266 mhz) at 633 mhz available in 2.5 clock cycle latency two input clocks (k and k ) for precise ddr timing ? sram uses rising edges only echo clocks (cq and cq ) simplify data capture in high speed systems data valid pin (qvld) to indi cate valid data on the output single multiplexed address input bus latches address inputs for read and write ports separate port selects for depth expansion synchronous internally self-timed writes qdr ? ii+ xtreme operates with 2.5 cycle read latency when doff is asserted high operates similar to qdr i device with one cycle read latency when doff is asserted low available in 18 and 36 configurations full data coherency, providing most current data core v dd = 1.8 v 0.1 v; i/o v ddq = 1.4 v to 1.6 v ? supports 1.5 v i/o supply hstl inputs and variable drive hstl output buffers available in 165-ball fbga package (13 15 1.4 mm) offered in pb-free packages jtag 1149.1 compatible test access port phase-locked loop (pll) for accurate data placement configurations with read cycle latency of 2.5 cycles: cy7c1563xv18 ? 4 m 18 cy7c1565xv18 ? 2 m 36 functional description the cy7c1563xv18, and cy7c1565xv18 are 1.8 v synchronous pipelined srams, equipped with qdr ii+ architecture. similar to qdr ii architecture, qdr ii+ architecture consists of two separate ports: the read port and the write port to access the memory array. the read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to supp ort write operations. qdr ii+ architecture has separate data inputs and data outputs to completely eliminate the need to ?turnaround? the data bus that exists with common i/o devices. each port is accessed through a common address bus. addresses for read and write addresses are latched on alternate rising edges of the input (k) clock. accesses to the qdr ii+ read and write ports are completely independent of one another. to maximize data throughput, both read and write ports are equipped with ddr interfaces. each address location is associated with four 18-bit words (cy7c1563xv18), or 36-bit words (cy7c1565xv18) that burst sequentially into or out of the device. because data is transferred into and out of the device on every rising edge of both input clocks (k and k ), memory bandwidth is maximized while simplifying system design by el iminating bus ?turnarounds?. depth expansion is accomplished with port selects, which enables each port to operate independently. all synchronous inputs pass through input registers controlled by the k or k input clocks. all data outputs pass through output registers controlled by the k or k input clocks. writes are conducted with on-chip synchron ous self-timed write circuitry. selection guide description 633 mhz 600 mhz unit maximum operating frequency 633 600 mhz maximum operating current 18 1165 1100 ma 36 1660 1570
cy7c1563xv18, cy7c1565xv18 document number: 001-70205 rev. *b page 2 of 29 logic block diagram ? cy7c1563xv18 logic block diagram ? cy7c1565xv18 1m x 18 array clk a (19:0) gen. k k control logic address register d [17:0] read add. decode read data reg. rps wps control logic address register reg. reg. reg. 36 20 72 18 bws [1:0] v ref write add. decode write reg 36 a (19:0) 20 1m x 18 array 1m x 18 array 1m x 18 array 18 cq cq doff q [17:0] qvld 18 18 18 write reg write reg write reg 18 512k x 36 array clk a (18:0) gen. k k control logic address register d [35:0] read add. decode read data reg. rps wps control logic address register reg. reg. reg. 72 19 144 36 bws [3:0] v ref write add. decode write reg 72 a (18:0) 19 512k x 36 array 512k x 36 array 512k x 36 array 36 cq cq doff q [35:0] qvld 36 36 36 write reg write reg write reg 36
cy7c1563xv18, cy7c1565xv18 document number: 001-70205 rev. *b page 3 of 29 contents pin configurations ........................................................... 4 pin definitions .................................................................. 5 functional overview ........................................................ 7 read operations ......................................................... 7 write operations ......................................................... 7 byte write operations ................................................. 7 concurrent transactions ..... ........................................ 7 depth expansion ......................................................... 8 programmable impedance ........ .............. ........... ......... 8 echo clocks .......... .............. .............. .............. ............ 8 valid data indicator (qvld) ........................................ 8 pll .............................................................................. 8 application example ........................................................ 8 truth table ........................................................................ 9 write cycle descriptions ................................................. 9 write cycle descriptions ............................................... 10 ieee 1149.1 serial boundary sc an (jtag) ... ........... .... 11 disabling the jtag feature ...................................... 11 test access port ....................................................... 11 performing a tap re set ........................................... 11 tap registers ........................................................... 11 tap instruction set ................................................... 11 tap controller state diagram ....................................... 13 tap controller block diagram ...................................... 14 tap electrical characteristics ...................................... 14 tap ac switching characteristics ............................... 15 tap timing and test conditions .................................. 16 identification register definitions ................................ 17 scan register sizes ....................................................... 17 instruction codes ........................................................... 17 boundary scan order .................................................... 18 power up sequence in qdr ii+ xtreme sram ............ 19 power up sequence ................................................. 19 pll constraints ......................................................... 19 maximum ratings ........................................................... 20 operating range ............................................................. 20 neutron soft error immunity ......................................... 20 electrical characteristics ............................................... 20 dc electrical characteristics ..................................... 20 over the operating range ........................................ 20 ac electrical characteristics ..................................... 21 capacitance .................................................................... 22 thermal resistance ........................................................ 22 ac test loads and waveforms ..................................... 22 switching characteristics .............................................. 23 switching waveforms .................................................... 24 read/write/deselect sequence ............. ........... ........ 24 ordering information ...................................................... 25 ordering code definitions ..... .................................... 25 package diagram ............................................................ 26 acronyms ........................................................................ 27 document conventions ................................................. 27 units of measure ....................................................... 27 document history page ................................................. 28 sales, solutions, and legal information ...................... 29 worldwide sales and design s upport ......... .............. 29 products .................................................................... 29 psoc solutions ......................................................... 29
cy7c1563xv18, cy7c1565xv18 document number: 001-70205 rev. *b page 4 of 29 pin configurations the pin configurations for cy7c1563 xv18, and cy7c1565xv18 follow. [1] figure 1. 165-ball fbga (13 15 1.4 mm) pinout cy7c1563xv18 (4 m 18) 1 2 3 4 5 6 7 8 9 10 11 a cq nc/144m a wps bws 1 k nc/288m rps aacq b nc q9 d9 a nc k bws 0 ancncq8 c nc nc d10 v ss ancav ss nc q7 d8 d nc d11 q10 v ss v ss v ss v ss v ss nc nc d7 e nc nc q11 v ddq v ss v ss v ss v ddq nc d6 q6 f nc q12 d12 v ddq v dd v ss v dd v ddq nc nc q5 g nc d13 q13 v ddq v dd v ss v dd v ddq nc nc d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc d14 v ddq v dd v ss v dd v ddq nc q4 d4 k nc nc q14 v ddq v dd v ss v dd v ddq nc d3 q3 l nc q15 d15 v ddq v ss v ss v ss v ddq nc nc q2 m nc nc d16 v ss v ss v ss v ss v ss nc q1 d2 n nc d17 q16 v ss aaav ss nc nc d1 p nc nc q17 a a qvld a a nc d0 q0 r tdotckaaancaaatmstdi cy7c1565xv18 (2 m 36) 1 2 3 4 5 6 7 8 9 10 11 a cq nc/288m a wps bws 2 k bws 1 rps a nc/144m cq b q27 q18 d18 a bws 3 kbws 0 ad17q17q8 c d27 q28 d19 v ss ancav ss d16 q7 d8 d d28 d20 q19 v ss v ss v ss v ss v ss q16 d15 d7 e q29 d29 q20 v ddq v ss v ss v ss v ddq q15 d6 q6 f q30 q21 d21 v ddq v dd v ss v dd v ddq d14 q14 q5 g d30 d22 q22 v ddq v dd v ss v dd v ddq q13 d13 d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j d31 q31 d23 v ddq v dd v ss v dd v ddq d12 q4 d4 k q32 d32 q23 v ddq v dd v ss v dd v ddq q12 d3 q3 l q33 q24 d24 v ddq v ss v ss v ss v ddq d11 q11 q2 m d33 q34 d25 v ss v ss v ss v ss v ss d10 q1 d2 n d34 d26 q25 v ss aaav ss q10 d9 d1 p q35 d35 q26 a a qvld a a q9 d0 q0 r tdotckaaancaaatmstdi note 1. nc/144m and nc/288m are not connected to the die and can be tied to any voltage level.
cy7c1563xv18, cy7c1565xv18 document number: 001-70205 rev. *b page 5 of 29 pin definitions pin name i/o pin description d [x:0] input- synchronous data input signals . sampled on the rising edge of k and k clocks when valid write operations are active. cy7c1563xv18 ? d [17:0] cy7c1565xv18 ? d [35:0] wps input- synchronous write port select ? active low . sampled on the rising edge of the k clock. when asserted active, a write operation is initiated. deasserting deselects the write port. deselecting the write port ignores d [x:0] . bws 0 , bws 1 , bws 2 , bws 3 input- synchronous byte write select 0, 1, 2, and 3 ? active low . sampled on the rising edge of the k and k clocks when write operations are active. used to select which byte is written into the device during the current portion of the write operations. bytes not written remain unaltered. cy7c1563xv18 ? bws 0 controls d [8:0] and bws 1 controls d [17:9]. cy7c1565xv18 ? bws 0 controls d [8:0] , bws 1 controls d [17:9] , bws 2 controls d [26:18] and bws 3 controls d [35:27]. all the byte write selects are sampled on the same edge as the data. deselecting a byte write select ignores the corresponding byte of data and it is not written into the device . a input- synchronous address inputs . sampled on the rising edge of the k clock during active read and write operations. these address inputs are multiplexed for both read and write operations. internally, the device is organized as 4 m 18 (4 arrays each of 1 m 18) for cy7c1563xv18 and 2 m 36 (4 arrays each of 512 k 36) for cy7c1565xv18. therefore, only 20 address inputs are needed to access the entire memory array for cy7c1563xv18 and 19 address inputs for cy7c1565xv18. these inputs are ignored when the appropriate port is deselected. the address pins (a) can be assigned any bit order. q [x:0] outputs- synchronous data output signals . these pins drive out the requested data when the read operation is active. valid data is driven out on the rising edge of the k and k clocks during read operations. on deselecting the read port, q [x:0] are automatically tristated. cy7c1563xv18 ? q [17:0] cy7c1565xv18 ? q [35:0] rps input- synchronous read port select ? active low . sampled on the rising edge of pos itive input clock (k). when active, a read operation is initiated. deasserting deselect s the read port. when deselected, the pending access is allowed to complete and the output drivers are au tomatically tristated followi ng the next rising edge of the k clock. each read access consists of a burst of four sequential transfers. qvld valid output indicator valid output indicator . the q valid indicates valid output dat a. qvld is edge aligned with cq and cq . k input clock positive input clock input . the rising edge of k is used to capture synchronous inputs to the device and to drive out data through q [x:0] . all accesses are initiated on the rising edge of k. k input clock negative input clock input . k is used to capture synchronous inputs being presented to the device and to drive out data through q [x:0] . cq echo clock synchronous echo clock outputs . this is a free running clock and is synchronized to the input clock (k) of the qdr ii+. the timings fo r the echo clocks are shown in the switching characteristics on page 23 . cq echo clock synchronous echo clock outputs . this is a free running clock and is synchronized to the input clock (k ) of the qdr ii+.the ti mings for the echo clocks are shown in the switching characteristics on page 23 . zq input output impedance matching input . this input is used to tune the device outputs to the system data bus impedance. cq, cq , and q [x:0] output impedance are set to 0.2 rq, where rq is a resistor connected between zq and ground. alternatively, this pin can be connected directly to v ddq , which enables the minimum impedance mode. this pin cannot be connected directly to gnd or left uncon- nected. doff input pll turn off ? active low . connecting this pin to ground turns off the pll inside the device. the timings in the pll turned off operation differs from those listed in this data sheet. for normal operation, this pin can be connected to a pull up through a 10 k ? or less pull up resistor. the device behaves in qdr i mode when the pll is turned off. in this mo de, the device can be operated at a frequency of up to 167 mhz with qdr i timing. tdo output tdo pin for jtag .
cy7c1563xv18, cy7c1565xv18 document number: 001-70205 rev. *b page 6 of 29 tck input tck pin for jtag . tdi input tdi pin for jtag . tms input tms pin for jtag . nc n/a not connected to the die . can be tied to any voltage level. nc /144m n/a not connected to the die . can be tied to any voltage level. nc /288m n/a not connected to the die . can be tied to any voltage level. v ref input- reference reference voltage input . static input used to set the reference level for hstl inputs, outputs, and ac measurement points. v dd power supply power supply inputs to the core of the device . v ss ground ground for the device . v ddq power supply power supply inputs for the outputs of the device . pin definitions (continued) pin name i/o pin description
cy7c1563xv18, cy7c1565xv18 document number: 001-70205 rev. *b page 7 of 29 functional overview the cy7c1563xv18 and cy7c1565xv18 are synchronous pipelined burst srams equipped with a read port and a write port. the read port is dedicated to read operations and the write port is dedicated to write operations. data flows into the sram through the write port and flows out through the read port. these devices multiplex the address inputs to minimize the number of address pins required. by having separate read and write ports, the qdr ii+ completely eliminates the need to ?turnaround? the data bus and avoids any possible data contention, thereby simplifying system design. each access consists of four 18-bit data transfers in the case of cy7c1563xv18, and four 36-bit data transfers in the case of cy7c1565xv18, in two clock cycles. these devices operate with a read latency of two and half cycles when doff pin is tied high. when doff pin is set low or connected to v ss then device behaves in qdr i mode with a read latency of one clock cycle. accesses for both ports are initiated on the positive input clock (k). all synchronous input and output timing are referenced from the rising edge of the input clocks (k and k ). all synchronous data inputs (d [x:0] ) pass through input registers controlled by the input clocks (k and k ). all synchronous data outputs (q [x:0] ) outputs pass through output registers controlled by the rising edge of the input clocks (k and k ) as well. all synchronous control (rps , wps , bws [x:0] ) inputs pass through input registers controlled by the rising edge of the input clocks (k and k ). cy7c1563xv18 is described in the following sections. the same basic descriptions apply to cy7c1565xv18. read operations the cy7c1563xv18 is organized internally as four arrays of 1 m 18. accesses are completed in a burst of four sequential 18-bit data words. read operat ions are initiated by asserting rps active at the rising edge of the positive input clock (k). the address presented to the address inputs is stored in the read address register. following the next two k clock rise, the corresponding lowest order 18-bit word of data is driven onto the q [17:0] using k as the output timing reference. on the subsequent rising edge of k, the next 18-bit data word is driven onto the q [17:0] . this process continues until all four 18-bit data words have been driven out onto q [17:0] . the requested data is valid 0.45 ns from the rising edge of the input clock (k or k ). to maintain the internal logic, each read access must be allowed to complete. each read access consists of four 18-bit data words and takes two clock cycles to complete. therefore, read accesses to the device can not be initiated on two consecutive k clock rises. the internal logic of the device ignores the second read request. read accesses can be initiated on every other k clock rise. doing so pipelines the data flow such that data is transferred out of the device on every rising edge of the input clocks (k and k ). when the read port is dese lected, the cy7c1563xv18 first completes the pending read transactions. synchronous internal circuitry automatically tristates the outputs following the next rising edge of the negative input clock (k ). this enables for a seamless transition between device s without the insertion of wait states in a depth expanded memory. write operations write operations are initiated by asserting wps active at the rising edge of the positive input clock (k). on the following k clock rise the data presented to d [17:0] is latched and stored into the lower 18-bit write data register, provided bws [1:0] are both asserted active. on the subsequent rising edge of the negative input clock (k ) the information presented to d [17:0] is also stored into the write data register, provided bws [1:0] are both asserted active. this process continues for one more cycle until four 18-bit words (a total of 72 bits) of data are stored in the sram. the 72 bits of data are then written into the memory array at the specified location. therefore, write accesses to the device can not be initiated on two consecutive k clock rises. the internal logic of the device ignores the second write request. write accesses can be initiated on every other rising edge of the positive input clock (k). doing so pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the in put clocks (k and k ). when deselected, the write port ignores all inputs after the pending write operations have been completed. byte write operations byte write operations are supp orted by the cy7c1563xv18. a write operation is initiated as described in the write operations section. the bytes that are written are determined by bws 0 and bws 1 , which are sampled with each set of 18-bit data words. asserting the appropriate byte wr ite select input during the data portion of a write latches the dat a being presented and writes it into the device. deasserting the byte write select input during the data portion of a write enab les the data stored in the device for that byte to remain unalte red. this feature can be used to simplify read, modify, or write operations to a byte write operation. concurrent transactions the read and write ports on the cy7c1563xv18 operates completely independently of one another. as each port latches the address inputs on different clock edges, the user can read or write to any location, regardless of the transaction on the other port. if the ports access the same location when a read follows a write in successive clock cycles, the sram delivers the most recent information associated with the specified address location. this includes forwarding data from a write cycle that was initiated on the previous k clock rise. read access and write access must be scheduled such that one transaction is initia ted on any clock cycle. if both ports are selected on the same k clock rise, the arbitration depends on the previous state of the sram. if both ports are deselected, the read port takes priority. if a read was initiated on the previous cycle, the write port takes priori ty (as read opera tions cannot be initiated on consecutive cycles). if a write was initiated on the previous cycle, the read port takes priority (as write operations can not be initia ted on consecutive cycles). therefore, asserting both port selects active from a deselected state results in alternating read or writ e operations being initiated, with the first access being a read.
cy7c1563xv18, cy7c1565xv18 document number: 001-70205 rev. *b page 8 of 29 depth expansion the cy7c1563xv18 has a port select input for each port. this enables for easy depth expansion. both port selects are sampled on the rising edge of the positive input clock only (k). each port select input can deselect the specified port. deselecting a port does not affect the other port. all pending transactions (read and write) are completed before the device is deselected. programmable impedance an external resistor, rq, must be connected between the zq pin on the sram and v ss to allow the sram to adjust its output driver impedance. the value of rq must be 5 the value of the intended line impedance driven by the sram, the allowable range of rq to guarantee impedance matching with a tolerance of 15% is between 175 ? and 350 ? , with v ddq =1.5 v. the output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature. echo clocks echo clocks are provided on the qdr ii+ to simplify data capture on high-speed systems. two echo clocks are generated by the qdr ii+. cq is referenced with respect to k and cq is referenced with respect to k . these are free running clocks and are synchronized to the input clock of the qdr ii+. the timing for the echo clocks is shown in the switching characteristics on page 23 . valid data indicator (qvld) qvld is provided on the qdr ii+ to simplify data capture on high speed systems. the qvld is g enerated by the qdr ii+ device along with data output. this signal is also edge-aligned with the echo clock and follows the timing of any data pin. this signal is asserted half a cycle before valid data arrives. pll these chips use a pll that is designed to function between 120 mhz and the specified maximum clock frequency. during power up, when the doff is tied high, the pll is locked after 100 ? s of stable clock. the pll ca n also be reset by slowing or stopping the input clocks k and k for a minimum of 30 ns. however, it is not necessary to reset the pll to lock to the desired frequency. the pll automatically locks 100 ? s after a stable clock is presented. the pll may be disabled by applying ground to the doff pin. when the pll is turned off, the device behaves in qdr i mode (with one cycle latency and a longer access time). for information, refer to the application note, pll considerations in q drii/ddrii/q drii+/ddrii+ . application example figure 2 shows two qdr ii+ used in an application. figure 2. application example bus master (cpu or asic) data in data out address source k source k vt vt vt r r d a k sram #2 rq = 250 ohms zq cq/cq q k rps wps bws d a k sram #1 cq/cq q k rps wps bws rps wps bws clkin1/clkin1 r = 50ohms, vt = v /2 ddq r rq = 250 ohms zq r clkin2/clkin2
cy7c1563xv18, cy7c1565xv18 document number: 001-70205 rev. *b page 9 of 29 truth table the truth table for cy7c1563xv18, and cy7c1565xv18 follows. [2, 3, 4, 5, 6, 7] operation k rps wps dq dq dq dq write cycle: load address on the rising edge of k; input write data on two consecutive k and k rising edges. l?h h [8] l [9] d(a) at k(t + 1) ? d(a + 1) at k (t + 1) ? d(a + 2) at k(t + 2) ? d(a + 3) at k (t + 2) ? read cycle: (2.5 cycle latency) load address on the rising edge of k; wait two and half cycles; read data on two consecutive k and k rising edges. l?h l [9] x q(a) at k (t + 2) ? q(a + 1) at k(t + 3) ? q(a + 2) at k (t + 3) ? q(a + 3) at k(t + 4) ? nop: no operation l?h h h d = x q = high z d = x q = high z d = x q = high z d = x q = high z standby: clock stopped stopped x x previous state previous state previous state previous state write cycle descriptions the write cycle description tabl e for cy7c1563xv18 follows. [2, 10] bws 0 bws 1 k k comments l l l?h ? during the data portion of a write sequence ? cy7c1563xv18 ?? both bytes (d [17:0] ) are written into the device. l l ? l?h during the data portion of a write sequence: cy7c1563xv18 ?? both bytes (d [17:0] ) are written into the device. l h l?h ? during the data portion of a write sequence: cy7c1563xv18 ?? only the lower byte (d [8:0] ) is written into the device, d [17:9] remains unaltered. l h ? l?h during the data portion of a write sequence ? cy7c1563xv18 ?? only the lower byte (d [8:0] ) is written into the device, d [17:9] remains unaltered. h l l?h ? during the data portion of a write sequence ? cy7c1563xv18 ?? only the upper byte (d [17:9] ) is written into the device, d [8:0] remains unaltered. h l ? l?h during the data portion of a write sequence ? cy7c1563xv18 ?? only the upper byte (d [17:9] ) is written into the device, d [8:0] remains unaltered. h h l?h ? no data is written into the devices during this portion of a write operation. h h ? l?h no data is written into the devices during this portion of a write operation. notes 2. x = ?don't care,? h = logic high, l = logic low, ? represents rising edge. 3. device powers up deselected with the outputs in a tristate condition. 4. ?a? represents address location latched by the devices when transaction was initiated. a + 1, a + 2, and a + 3 represents the address sequence in the burst. 5. ?t? represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the ?t? clock cycle. 6. data inputs are registered at k and k rising edges. data outputs are delivered on k and k rising edges as well. 7. it is recommended that k = k = high when clock is stopped. this is not essential, but permi ts most rapid restart by overcoming transmission line charging s ymmetrically. 8. if this signal was low to initiate the previous cycle , this signal becomes a ?don? t care? for this operation. 9. this signal was high on previous k clock rise. initiating cons ecutive read or write operations on consecutive k clock rises i s not permitted. the device ignores the second read or write request. 10. is based on a write cycle that was initiated in accordance with above truth table . bws 0 , bws 1 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved.
cy7c1563xv18, cy7c1565xv18 document number: 001-70205 rev. *b page 10 of 29 write cycle descriptions the write cycle description ta ble for cy7c1565xv18 follows. [11, 12] bws 0 bws 1 bws 2 bws 3 k k comments lllll?h?during the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. llll?l?hduring the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. l h h h l?h ? during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] remains unaltered. l h h h ? l?h during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] remains unaltered. h l h h l?h ? during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] remains unaltered. h l h h ? l?h during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] remains unaltered. h h l h l?h ? during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] remains unaltered. h h l h ? l?h during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] remains unaltered. h h h l l?h ? during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] remains unaltered. h h h l ? l?h during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] remains unaltered. hhhhl?h?no data is written into the device during this portion of a write operation. hhhh?l?hno data is written into the device during this portion of a write operation. notes 11. x = ?don't care,? h = logic high, l = logic low, ? represents rising edge. 12. is based on a write cycle that was initiated in accordance with above truth table on page 9 . bws 0 , bws 1 can be altered on different port ions of a write cycle, as long as the setup and hold requirements are achieved.
cy7c1563xv18, cy7c1565xv18 document number: 001-70205 rev. *b page 11 of 29 ieee 1149.1 serial boundary scan (jtag) these srams incorporate a serial boundary scan test access port (tap) in the fbga package. th is part is fully compliant with ieee standard #1149. 1-2001. the tap operates using jedec standard 1.8 v i/o logic levels. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap co ntroller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconnected. they may alternatively be connected to v dd through a pull up resistor. tdo must be left unconnected. upon power up, the device comes up in a reset state, which does not interfere with the operation of the device. test access port test clock the test clock is used only with the tap controller. all inputs are captured on the rising edge of tc k. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. this pin may be left unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see tap controller state diagram on page 13 . tdi is internally pulled up and can be unconnected if the tap is unus ed in an application. tdi is connected to the most signific ant bit (msb) on any register. test data-out (tdo) the tdo output pin is used to serially clock data out from the registers. the output is active, depending upon the current state of the tap state machine (see instruction codes on page 17 ). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and can be performed while the sram is operating. at power up, the tap is reset intern ally to ensure that tdo comes up in a high z state. tap registers registers are connected between the tdi and tdo pins to scan the data in and out of the sram te st circuitry. only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins, as shown in tap controller block diagram on page 14 . upon power up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is pl aced in a reset state, as described in the previous section. when the tap controller is in th e capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this enables shifting of data through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all of the input and output pins on the sram. several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload, and sa mple z instructions can be used to capture the contents of the input and output ring. the section boundary scan order on page 18 shows the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register . the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id regist er has a vendor code and other information described in identification register definitions on page 17 . tap instruction set eight different instructions ar e possible with the three-bit instruction register. all co mbinations are listed in instruction codes on page 17 . three of these instru ctions are listed as reserved and must not be used. the other five instructions are described in this section in detail. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo pins. to execute the instruction after it is shift ed in, the tap controller must be moved into the update-ir state.
cy7c1563xv18, cy7c1565xv18 document number: 001-70205 rev. *b page 12 of 29 idcode the idcode instruction loads a vendor-specific, 32-bit code into the instruction register. it also places the instruction register between the tdi and tdo pins and shifts the idcode out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register at power up or whenever the tap controller is supplied a test-logic-reset state. sample z the sample z instruction connects the boundary scan register between the tdi and tdo pins when the tap controller is in a shift-dr state. the sample z command puts the output bus into a high z state until the next command is supplied during the update ir state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instructions are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the input and output pins is captured in the boundary scan register. the tap controller clock can on ly operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output undergoes a transi tion. the tap may then try to capture a signal while in transition (metastable state). this does not harm the device, but there is no guarantee as to the value that is captured. repeatable results may not be possible. to guarantee that the boundary scan register captures the correct value of a signal, the sram signal must be stabilized long enough to meet the tap cont roller?s capture setup plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a de sign to stop (or slow) the clock during a sample/preload instructi on. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. after the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. preload places an initial data pattern at the latched parallel outputs of the boundary scan regi ster cells before the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when requir ed, that is, while the data captured is shifted out, the pr eloaded data can be shifted in. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift- dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. extest the extest instruction drives the preloaded data out through the system output pins. this instruction also connects the boundary scan register for serial access between the tdi and tdo in the shift-dr controller state. extest output bus tristate ieee standard 1149.1 mandates that the tap controller be able to put the output bus into a tristate mode. the boundary scan register has a special bit located at bit #108. when this scan cell, called the ?extest output bus tristate,? is latched into the preload register during the update-dr state in the tap controller, it directly controls the state of the output (q-bus) pins, when the extest is entered as the current instruction. when high, it enables the output buffers to drive the output bus. when low, this bi t places the output bus into a high z condition. this bit can be set by entering the sample/preload or extest command, and then shifting the desired bit into that cell, during the shift-dr state. during update-dr, the value loaded into that shift-register cell latc hes into the preload register. when the extest instruction is entered, this bit directly controls the output q-bus pins. note that this bit is preset high to enable the output when the device is power ed up, and also when the tap controller is in the test-logic-reset state. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions.
cy7c1563xv18, cy7c1565xv18 document number: 001-70205 rev. *b page 13 of 29 tap controller state diagram the state diagram for the tap controller follows. [13] test-logic reset test-logic/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 select ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir note 13. the 0/1 next to each state represents the value at tms at the rising edge of tck.
cy7c1563xv18, cy7c1565xv18 document number: 001-70205 rev. *b page 14 of 29 tap controller block diagram 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . 108 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tck tms tap electrical characteristics over the operating range parameter [14, 15, 16] description test conditions min max unit v oh1 output high voltage i oh = ?? 2.0 ma 1.4 ? v v oh2 output high voltage i oh = ?? 100 ? a1.6?v v ol1 output low voltage i ol = 2.0 ma ? 0.4 v v ol2 output low voltage i ol = 100 ? a?0.2v v ih input high voltage 0.65 v dd v dd + 0.3 v v il input low voltage ?0.3 0.35 v dd v i x input and output load current gnd ? v i ? v dd ?5 5 ? a notes 14. these characteristics pertain to the tap inputs (tms, tck, tdi and tdo). parallel load levels are specified in the electrical characteristics on page 20 . 15. overshoot: v ih(ac) < v ddq + 0.35 v (pulse width less than t cyc /2), undershoot: v il(ac) > ? 0.3 v (pulse width less than t cyc /2). 16. all voltage referenced to ground.
cy7c1563xv18, cy7c1565xv18 document number: 001-70205 rev. *b page 15 of 29 tap ac switchi ng characteristics over the operating range parameter [17, 18] description min max unit t tcyc tck clock cycle time 50 ? ns t tf tck clock frequency ? 20 mhz t th tck clock high 20 ? ns t tl tck clock low 20 ? ns setup times t tmss tms setup to tck clock rise 5 ? ns t tdis tdi setup to tck clock rise 5 ? ns t cs capture setup to tck rise 5 ? ns hold times t tmsh tms hold after tck clock rise 5 ? ns t tdih tdi hold after clock rise 5 ? ns t ch capture hold after clock rise 5 ? ns output times t tdov tck clock low to tdo valid ? 10 ns t tdox tck clock low to tdo invalid 0 ? ns notes 17. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 18. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns.
cy7c1563xv18, cy7c1565xv18 document number: 001-70205 rev. *b page 16 of 29 tap timing and test conditions figure 3 shows the tap timing and test conditions. [19] figure 3. tap timing and test conditions t tl t th (a) tdo c l = 20 pf z 0 = 50 ? gnd 0.9v 50 ? 1.8v 0v all input pulses 0.9v test clock test mode select tck tms test data in tdi test data out t tcyc t tmsh t tmss t tdis t tdih t tdov t tdox tdo note 19. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns.
cy7c1563xv18, cy7c1565xv18 document number: 001-70205 rev. *b page 17 of 29 identification regi ster definitions instruction field value description cy7c1563xv18 cy7c1565xv18 revision number (31:29) 000 000 version number. cypress device id (28:12) 11010010001010100 1 1010010001100100 defines the type of sram. cypress jedec id (11:1) 00000110100 00000110100 allows unique identification of sram vendor. id register presence (0) 1 1 indicates the presence of an id register. scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan 109 instruction codes instruction code description extest 000 captures the input and output ring contents. idcode 001 loads the id register wit h the vendor id code and places the register between tdi and tdo. this operation does not affect sram operation. sample z 010 captures the input and output contents . places the boundary scan register between tdi and tdo. forces all sram output drivers to a high z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures the input and output ring co ntents. places the boundary scan register between tdi and tdo. does not affect the sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operation.
cy7c1563xv18, cy7c1565xv18 document number: 001-70205 rev. *b page 18 of 29 boundary scan order bit # bump id bit # bump id bit # bump id bit # bump id 0 6r 28 10g 56 6a 84 1j 16p299g575b852j 2 6n 30 11f 58 5a 86 3k 3 7p 31 11g 59 4a 87 3j 47n 329f 605c 882k 5 7r 33 10f 61 4b 89 1k 6 8r 34 11e 62 3a 90 2l 7 8p 35 10e 63 2a 91 3l 8 9r 36 10d 64 1a 92 1m 9 11p 37 9e 65 2b 93 1l 10 10p 38 10c 66 3b 94 3n 11 10n 39 11d 67 1c 95 3m 12 9p 40 9c 68 1b 96 1n 13 10m 41 9d 69 3d 97 2m 14 11n 42 11b 70 3c 98 3p 15 9m 43 11c 71 1d 99 2n 16 9n 44 9b 72 2c 100 2p 17 11l 45 10b 73 3e 101 1p 18 11m 46 11a 74 2d 102 3r 19 9l 47 10a 75 2e 103 4r 20 10l 48 9a 76 1e 104 4p 21 11k 49 8b 77 2f 105 5p 22 10k 50 7c 78 3f 106 5n 23 9j 51 6c 79 1g 107 5r 24 9k 52 8a 80 1f 108 internal 25 10j 53 7a 81 3g 26 11j 54 7b 82 2g 27 11h 55 6b 83 1h
cy7c1563xv18, cy7c1565xv18 document number: 001-70205 rev. *b page 19 of 29 power up sequence in qdr ii+ xtreme sram qdr ii+ xtreme srams must be powered up and initialized in a predefined manner to prevent undefined operations. power up sequence apply power and drive doff either high or low (all other inputs can be high or low). ? apply v dd before v ddq . ? apply v ddq before v ref or at the same time as v ref . ? drive doff high. provide stable doff (high), power and clock (k, k ) for 100 ? s to lock the pll. pll constraints pll uses k clock as its synchronizing input. the input must have low phase jitter, which is specified as t kc var . the pll functions at frequencies down to 120 mhz. if the input clock is unstable and the pll is enabled, then the pll may lock onto an incorrect frequency, causing unstable sram behavior. to avoid this, provide 100 ? s of stable clock to relock to the desired clock frequency. figure 4. power up waveforms
cy7c1563xv18, cy7c1565xv18 document number: 001-70205 rev. *b page 20 of 29 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ................ ............... ?65 c to +150 c supply voltage on v dd relative to gnd .....?0.5 v to +2.9 v supply voltage on v ddq relative to gnd .... ?0.5 v to +v dd dc applied to outputs in high z ...... ?0.5 v to v ddq + 0.3 v dc input voltage [20] ........................... ?0.5 v to v dd + 0.3 v current into outputs (low) ...... .................................. 20 ma static discharge voltage (mil-std-883, m. 3015) ....................................... > 2,001 v latch up current ................................................... > 200 ma maximum junction temperature.. ................................125 c operating range range ambient temperature (t a ) v dd [21] v ddq [21] commercial 0 c to +70 c 1.8 0.1 v 1.4 v to 1.6 v neutron soft error immunity parameter description test conditions typ max* unit lsbu logical single-bit upsets 25 c 260 271 fit/ mb lmbu logical multi-bit upsets 25 c 0 0.01 fit/ mb sel single event latch up 85 c 0 0.1 fit/ dev * no lmbu or sel events occurred during testing ; this column represents a statistical ? 2 , 95% confidence limit calculat ion. for more details refer to application note an54908 ?accelerated neutron ser testing and calculation of terrestrial failure rates? . electrical characteristics over the operating range dc electrical characteristics over the operating range parameter [22] description test conditions min typ max unit v dd power supply voltage 1.7 1.8 1.9 v v ddq i/o supply voltage 1.4 1.5 1.6 v v oh output high voltage note 23 v ddq /2 ? 0.12 ? v ddq /2 + 0.12 v v ol output low voltage note 24 v ddq /2 ? 0.12 ? v ddq /2 + 0.12 v v oh(low) output high voltage i oh = ?? 0.1 ma, nominal impedance v ddq ? 0.2 ? v ddq v v ol(low) output low voltage i ol = 0.1 ma, nominal impedance v ss ? 0.2 v v ih input high voltage v ref + 0.1 ? v ddq + 0.15 v v il input low voltage ?0.15 ? v ref ? 0.1 v i x input leakage current gnd ? v i ? v ddq ? 2 ? 2 ? a i oz output leakage current gnd ? v i ? v ddq, output disabled ? 2 ? 2 ? a v ref input reference voltage typical value = 0.75 v 0.68 0.75 0.86 v notes 20. overshoot: v ih(ac) < v ddq + 0.35 v (pulse width less than t cyc /2), undershoot: v il(ac) > ? 0.3 v (pulse width less than t cyc /2). 21. power up: assumes a linear ramp from 0 v to v dd(min) within 200 ms. during this time v ih < v dd and v ddq < v dd . 22. all voltage referenced to ground. 23. outputs are impedance controlled. i oh = ? (v ddq /2)/(rq/5) for values of 175 ohms < rq < 350 ohms. 24. outputs are impedance controlled. i ol = (v ddq /2)/(rq/5) for values of 175 ohms < rq < 350 ohms.
cy7c1563xv18, cy7c1565xv18 document number: 001-70205 rev. *b page 21 of 29 i dd [25] v dd operating supply v dd = max, i out = 0 ma, f = f max = 1/t cyc 633 mhz ( 18) ? ? 1165 ma ( 36) ? ? 1660 600 mhz ( 18) ? ? 1100 ma ( 36) ? ?1570 i sb1 automatic power down current max v dd , both ports deselected, v in ? v ih or v in ? v il , f = f max = 1/t cyc , inputs static 633 mhz ( 18) ? ? 1165 ma ( 36) ? ? 1660 600 mhz ( 18) ? ? 1100 ma ( 36) ? ? 1570 electrical characteristics (continued) over the operating range dc electrical characteristics (continued) over the operating range parameter [22] description test conditions min typ max unit ac electrical characteristics over the operating range parameter [26] description test conditions min typ max unit v ih input high voltage v ref + 0.2 ? v ddq + 0.24 v v il input low voltage ?0.24 ? v ref ? 0.2 v notes 25. the operation current is calculated with 50% read cycle and 50% write cycle. 26. overshoot: v ih(ac) < v ddq + 0.35 v (pulse width less than t cyc /2), undershoot: v il(ac) > ? 0.3 v (pulse width less than t cyc /2).
cy7c1563xv18, cy7c1565xv18 document number: 001-70205 rev. *b page 22 of 29 capacitance parameter [27] description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v dd = 1.8 v, v ddq = 1.5 v 4 pf c o output capacitance 4pf thermal resistance parameter [27] description test conditions 165-ball fbga package unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. with still air (0 m/s) 23.94 c/w ? jc thermal resistance (junction to case) 3.00 c/w ac test loads and waveforms figure 5. ac test loads and waveforms 1.25 v 0.25 v r = 50 ? 5pf including jig and scope all input pulses device r l = 50 ? z 0 = 50 ? v ref = 0.75 v v ref = 0.75 v [28] 0.75 v under te s t 0.75 v device under te s t output 0.75 v v ref v ref output zq zq (a) slew rate = 2 v/ns rq = 250 ? (b) rq = 250 ? 27. tested initially and after any design or proc ess change that may affect these parameters. 28. unless otherwise noted, test conditions are based on signal trans ition time of 2 v/ns, timing reference levels of 0.75 v, vr ef = 0.75 v, rq = 250 ? , v ddq = 1.5 v, input pulse levels of 0.25 v to 1.25 v, and output loading of the specified i ol /i oh and load capacitance shown in (a) of figure 5 .
cy7c1563xv18, cy7c1565xv18 document number: 001-70205 rev. *b page 23 of 29 switching characteristics over the operating range parameter [29, 30] description 633 mhz 600 mhz unit cypress parameter consortium parameter min max min max t power v dd (typical) to the first access [31] 1?1?ms t cyc t khkh k clock cycle time 1.58 8.4 1.66 8.4 ns t kh t khkl input clock (k/k ) high 0.4?0.4?ns t kl t klkh input clock (k/k ) low 0.4?0.4?ns t khk h t khk h k clock rise to k clock rise (rising edge to rising edge) 0.71 ? 0.75 ? ns setup times t sa t avkh address setup to k clock rise 0.23 ? 0.23 ? ns t sc t ivkh control setup to k clock rise (rps , wps ) 0.23 ? 0.23 ? ns t scddr t ivkh double data rate cont rol setup to clock (k/k ) rise (bws 0 , bws 1 , bws 2 , bws 3 ) 0.18 ? 0.18 ? ns t sd t dvkh d [x:0] setup to clock (k/k ) rise 0.18 ? 0.18 ? ns hold times t ha t khax address hold after k clock rise 0.23 ? 0.23 ? ns t hc t khix control hold after k clock rise (rps , wps ) 0.23 ? 0.23 ? ns t hcddr t khix double data rate contro l hold after clock (k/k ) rise (bws 0 , bws 1 , bws 2 , bws 3 ) 0.18 ? 0.18 ? ns t hd t khdx d [x:0] hold after clock (k/k ) rise 0.18 ? 0.18 ? ns output times t ccqo t chcqv k/k clock rise to echo clock valid ? 0.45 ? 0.45 ns t cqoh t chcqx echo clock hold after k/k clock rise ?0.45 ? ?0.45 ? ns t cqd t cqhqv echo clock high to data valid ? 0.09 ? 0.09 ns t cqdoh t cqhqx echo clock high to data invalid ?0.09 ? ?0.09 ? ns t cqh t cqhcql output clock (cq/cq ) high [32] 0.71 ? 0.75 ? ns t cqhcq h t cqhcq h cq clock rise to cq clock rise (rising edge to rising edge) [32] 0.71 ? 0.75 ? ns t chz t chqz clock (k/k ) rise to high z (a ctive to high z) [33, 34] ? 0.45 ? 0.45 ns t clz t chqx1 clock (k/k ) rise to low z [33, 34] ?0.45 ? ?0.45 ? ns t qvld t cqhqvld echo clock high to qvld valid [35] ?0.15 0.15 ?0.15 0.15 ns pll timing t kc var t kc var clock phase jitter ? 0.15 ? 0.15 ns t kc lock t kc lock pll lock time (k) 100 ? 100 ? ? s t kc reset t kc reset k static to pll reset [36] 30?30?ns notes 29. unless otherwise noted, test conditions are based on signal tr ansition time of 2 v/ns, timing reference levels of 0.75 v, vr ef = 0.75 v, rq = 250 ? , v ddq = 1.5 v, input pulse levels of 0.25 v to 1.25 v, and output loading of the specified i ol /i oh and load capacitance shown in (a) of figure 5 on page 22 . 30. when a part with a maximum frequency above 600 mhz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range. 31. this part has a voltage regulator internally; t power is the time that the power must be supplied above v dd(minimum) initially before a read or write operation can be initiated. 32. these parameters are extrapolated from the input timing parameters (t cyc /2 ? 80 ps, where 80 ps is the internal jitter). these parameters are only guaranteed by design and are not tested in production. 33. t chz , t clz , are specified with a load capacitance of 5 pf as in (b) of figure 5 on page 22 . transition is measured 100 mv from steady-state voltage. 34. at any voltage and temperature t chz is less than t clz . 35. t qvld spec is applicable for both rising and falling edges of qvld signal. 36. hold to >v ih or cy7c1563xv18, cy7c1565xv18 document number: 001-70205 rev. *b page 24 of 29 switching waveforms read/write/deselect sequence figure 6. waveform for 2.5 cycle read latency [37, 38, 39] notes 37. q00 refers to output from address a0. q01 refers to output from the next internal burst address following a0, that is, a0 + 1. 38. outputs are disabled (high z) one clock cycle after a nop. 39. in this example, if address a2 = a1, then data q20 = d10, q21 = d11, q22 = d12, and q23 = d13. write data is forwarded immed iately as read results. this note applies to the whole diagram.
cy7c1563xv18, cy7c1565xv18 document number: 001-70205 rev. *b page 25 of 29 ordering information cypress offers other versions of this type of product in many different configurations an d features. the below table contains o nly the list of parts that are currently available. for a complete listing of all options, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypre ss.com/products or contact your loca l sales representative. cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representativ es and distributors. to find th e office closest to you, visit us at http://app.cypress.com/portal/server.pt?space=c ommunitypage&control=set community&communityid= 201&pageid=230 . ordering code definitions speed (mhz) ordering code package diagram package type operating range 633 CY7C1563XV18-633BZXC 51-85180 165-ball fbga (13 15 1.4 mm) pb-free commercial cy7c1565xv18-633bzxc 600 cy7c1563xv18-600bzxc 51-85180 165-ball fbga (13 15 1.4 mm) pb-free commercial cy7c1565xv18-600bzxc temperature range: c = commercial pb-free package type: bz = 165-ball fbga frequency range: xxx = 633 mhz or 600 mhz v18 = 1.8 v die revision part identifier: 156x = 1563 or 1565 technology code: c = cmos marketing code: 7 = sram company id: cy = cypress 7 cy 156x x - xxx bz x v18 c x
cy7c1563xv18, cy7c1565xv18 document number: 001-70205 rev. *b page 26 of 29 package diagram figure 7. 165-ball fbga (13 15 1.4 mm) bb165d/bw 165d (0.5 ball diameter) package outline, 51-85180 51-85180 *e
cy7c1563xv18, cy7c1565xv18 document number: 001-70205 rev. *b page 27 of 29 acronyms document conventions units of measure acronym description ddr double data rate fbga fine-pitch ball grid array hstl high-speed transceiver logic i/o input/output jtag joint test action group lmbu logical multi-bit upsets lsb least significant bit lsbu logical single-bit upsets msb most significant bit pll phase-locked loop qdr quad data rate sel single event latch-up sram static random access memory tap test access port tck test clock tms test mode select tdi test data-in tdo test data-out symbol unit of measure c degree celsius k ? kilohm mhz megahertz a microampere s microsecond ma milliampere mv millivolt mm millimeter ms millisecond ns nanosecond ? ohm % percent pf picofarad ps picosecond vvolt wwatt
cy7c1563xv18, cy7c1565xv18 document number: 001-70205 rev. *b page 28 of 29 document history page document title: cy7c1563xv18/cy7c1565xv18, 72-mbit qdr ? ii+ xtreme sram four-word burst architecture (2.5 cycle read latency) document number: 001-70205 rev. ecn orig. of change submission date description of change ** 3304141 osn 07/06/2011 new data sheet. *a 3532349 prit 02/22/2012 changed stat us from preliminary to final. *b 3653401 prit 06/22/2012 no technical updates.
document number: 001-70205 rev. *b revised june 22, 2012 page 29 of 29 qdr rams and quad data rate rams comprise a new family of products developed by cypress, idt, nec, renesas, and samsung. all pr oducts and company names mentioned in this document may be the trademarks of their respective holders. cy7c1563xv18, cy7c1565xv18 ? cypress semiconductor corporation, 2011-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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